How does a processor run a program, one instruction at a time, using the fetch-execute cycle?
Describe the fetch-decode-execute cycle, the registers involved, and how the program counter sequences instructions
A focused answer to the H2 Computing outcome on the fetch-execute cycle. The fetch, decode and execute stages, the program counter, memory address and data registers, the instruction register, and how branching changes the flow.
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What this dot point is asking
SEAB wants you to describe the fetch-decode-execute cycle, the registers it uses, and how the program counter sequences instructions including on a branch. The central idea is that a processor runs a program by repeating one simple loop - fetch the next instruction, decode it, execute it - and that the program counter is what keeps track of where it is up to.
The answer
The cycle
A CPU executes a program by repeating the fetch-decode-execute cycle:
- Fetch - copy the next instruction from memory into the CPU.
- Decode - the control unit interprets the instruction: what operation, on what operands.
- Execute - carry out the operation (an arithmetic or logic step in the ALU, a data transfer, or a change of control flow).
The cycle then repeats with the next instruction, billions of times per second.
The registers involved
Several special registers drive the cycle:
- Program counter (PC) - holds the memory address of the next instruction.
- Memory address register (MAR) - holds the address currently being accessed in memory.
- Memory data register (MDR) - holds data just read from or about to be written to memory.
- Instruction register (IR) - holds the current instruction while it is decoded and executed.
- Accumulator (ACC) - holds intermediate results of calculations.
A fetch in detail
During fetch: the address in the PC is copied to the MAR; memory returns the instruction into the MDR; the instruction is transferred to the IR; and the PC is incremented to point to the following instruction. Incrementing early means the PC is already set for the next fetch before the current instruction executes.
Sequencing and branching
Normally instructions run in sequence because the PC increments each cycle. A branch (jump) instruction changes this: during execute it loads a new target address into the PC, so the next fetch comes from the branch destination. This single mechanism implements loops and selection - the program counter is simply overwritten to redirect the flow.
Examples in context
Example 1. A loop in machine code. A loop that repeats ten times ends with a conditional branch back to its start. Each pass, the cycle executes the body instruction by instruction with the PC incrementing, until the branch overwrites the PC with the loop's start address - or, when the count is reached, lets the PC fall through to the next instruction.
Example 2. Clock speed and instruction throughput. A processor's clock speed sets how many cycle steps it performs per second, so a faster clock runs more fetch-decode-execute cycles and thus more instructions per second. This is why clock speed (alongside how much work each instruction does) is a headline measure of CPU performance.
Try this
Q1. Name the three stages of the fetch-decode-execute cycle. [1 mark]
- Cue. Fetch, decode, execute.
Q2. What does the program counter hold, and how does it change on a branch instruction? [2 marks]
- Cue. It holds the address of the next instruction; a branch loads a target address into it, so the next fetch comes from the branch destination.
Q3. State the difference between the MAR and the MDR. [2 marks]
- Cue. The MAR holds the memory address being accessed; the MDR holds the data (or instruction) being read from or written to memory.
Exam-style practice questions
Practice questions written in the style of SEAB exam questions on this dot point, with worked answer explainers. The year tag is the paper they imitate, not the source.
Original6 marks(a) Describe the three stages of the fetch-decode-execute cycle. (b) State the role of the program counter (PC) and the memory address register (MAR) during the fetch stage. (c) What is loaded into the instruction register (IR)?Show worked answer →
(a) The three stages:
- Fetch - the next instruction is copied from memory into the CPU.
- Decode - the control unit interprets the instruction to determine the operation and its operands.
- Execute - the operation is carried out (for example, an arithmetic operation in the ALU, or a data transfer).
(b) During fetch, the program counter (PC) holds the memory address of the next instruction. That address is copied into the memory address register (MAR), which addresses memory; the PC is then incremented to point to the following instruction.
(c) The fetched instruction (transferred via the memory data register) is loaded into the instruction register (IR), where it is held while it is decoded and executed.
Markers reward the three named stages with correct descriptions, the PC holding the next address copied to the MAR (and the PC incrementing), and the fetched instruction held in the IR.
Original5 marks(a) Explain how the program counter is normally updated during the cycle, and what happens to it when a branch (jump) instruction executes. (b) Explain why the program counter is incremented during the fetch stage rather than after execution.Show worked answer →
(a) Normally the program counter is incremented during each cycle so it points to the next instruction in sequence. When a branch (jump) instruction executes, the target address is loaded into the program counter instead, so the next fetch comes from the branch destination rather than the next sequential instruction. This is how loops and selection change the flow of control.
(b) Incrementing the PC during fetch (right after its address has been used) means the PC already points to the next instruction before the current one executes. This keeps sequencing correct even though execution may take varying time, and lets a branch instruction during execute simply overwrite the PC with a new target - so a branch naturally redirects the next fetch without extra steps.
Markers reward the PC incrementing for sequential flow and being overwritten with the target on a branch, and the reasoning that early incrementing leaves the PC ready so a branch can cleanly replace it.
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